K60P100M100SF2RM Datasheet, PDF (1695/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
0
TFE0
Chapter 53 Integrated interchip sound (I2S)
I2Sx_ISR field descriptions (continued)
Transmit FIFO Empty 0.
Description
This flag is set when the empty slots in Tx FIFO exceed or are equal to the selected Tx FIFO WaterMark
0 (TFWM0) threshold. The setting of TFE0 only causes an interrupt when IER[TIE] and IER[TFE0EN] are
set and Tx FIFO0 is enabled. The TFE0 bit is automatically cleared when the data level in Tx FIFO0
becomes more than the amount specified by the watermark bits. The TFE0 bit is set by POR and I²S
reset.
0 Transmit FIFO0 has data for transmission.
1 Transmit FIFO0 is empty.
53.3.7 I²S Interrupt Enable Register (I2Sx_IER)
The I2S interrupt enable register (IER) is a 25-bit register used to set up the I2S interrupts
and DMA requests.
Addresses: I2S0_IER is 4002_F000h base + 18h offset = 4002_F018h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
RIE
TIE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset 0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
I2Sx_IER field descriptions
Field
31–25
Reserved
24
RFRC_EN
Description
This read-only field is reserved and always has the value zero.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
23
TFRC_EN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1695