K60P100M100SF2RM Datasheet, PDF (1424/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
49.4.3.3 After SCK Delay (t_ASC)
The After SCK Delay is the length of time between the last edge of SCK and the negation
of PCS. See Figure 49-94 and Figure 49-95 for illustrations of the After SCK delay. The
PASC and ASC fields in the CTARx registers select the After SCK Delay by the formula
in the ASC field description. The following table shows an example of how to compute
the After SCK delay.
Table 49-108. After SCK Delay Computation Example
f_sys
100 MHz
PASC
0b01
Prescaler
3
ASC
0b0100
Scaler
32
After SCK Delay
0.96 μs
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
49.4.3.4 Delay after Transfer (t_DT)
The Delay after Transfer is the minimum time between negation of the PCS signal for a
frame and the assertion of the PCS signal for the next frame. See Figure 49-94 for an
illustration of the Delay after Transfer. The PDT and DT fields in the CTARx registers
select the Delay after Transfer by the formula in the DT field description. The following
table shows an example of how to compute the Delay after Transfer.
Table 49-109. Delay after Transfer Computation Example
f_sys
100 MHz
PDT
0b01
Prescaler
3
DT
0b1110
Scaler
32768
Delay after Transfer
0.98 ms
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
When in non-continuous clock mode the t_DT delay is configured according to the
equation specified in the CTAR[DT] bitfield description. When in continuous clock
mode, the delay is fixed at 1 SCK period.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.