K60P100M100SF2RM Datasheet, PDF (559/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 24 Multipurpose Clock Generator (MCG)
24.4.6 MCG PLL Clock
The MCG PLL Clock (MCGPLLCLK) is available depending on the device's
configuration of the MCG module. For more details, refer to the clock distribution
chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until
it is enabled and S[LOCK] is set.
24.4.7 MCG Auto TRIM (ATM)
The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG
hardware to automatically trim the MCG Internal Reference Clocks using an external
clock as a reference. The selection between which MCG IRC clock gets tested and
enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz
IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM,
a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz.
When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will
start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME]
will remain asserted and will deassert after ATM is completed or an abort occurs. The
MCG ATM is aborted if a write to any of the following control registers is detected
including: C1, C3, C4, or ATC or if Stop mode is entered. If an abort occurs,
ATC[ATMF] fail flag is asserted.
The ATM machine uses the bus clock as the external reference clock to perform the IRC
auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the
reference clock used to generate the system clock is the external reference clock such as
FBE clock mode. The MCG must not be configured in a clock mode where selected IRC
ATM clock is used to generate the system clock. The bus clock is also required to be
running with in the range of 8 - 16 MHz.
To perform the ATM on the selected IRC, the ATM machine uses the successive
approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed
frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For
each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock
to enable a counter that counts number of ATM external clocks. At end of each trim bit,
the ATM external counter value is compared to the ATCV[15:0] register value. Based on
the comparison result, the ATM trim bit under test will get cleared or stay asserted. This
is done until all trim bits have been tested by ATM SAR machine.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
559