K60P100M100SF2RM Datasheet, PDF (846/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization information
CFG1 = 0x98 (%10011000)
Bit 7 ADLPC 1
Bit 6:5 ADIV 00
Bit 4 ADLSMP 1
Bit 3:2 MODE 10
bit conversion.
Bit 1:0 ADICLK 00
Configures for low power (lowers maximum clock speed.
Sets the ADCK to the input clock ÷ 1.
Configures for long sample time.
Selects the single-ended 10-bit conversion, differential 11-
Selects the bus clock.
SC2 = 0x00 (%00000000)
Bit 7 ADACT 0
Bit 6 ADTRG 0
Bit 5 ACFE 0
Bit 4 ACFGT 0
Bit 3 ACREN 0
Bit 2 DMAEN 0
Bit 1:0 REFSEL 00
and V_REFL).
Flag indicates if a conversion is in progress.
Software trigger selected.
Compare function disabled.
Not used in this example.
Compare range disabled.
DMA request disabled.
Selects default voltage reference pin pair (External pins V_REFH
SC1A = 0x41 (%01000001)
Bit 7 COCO
Bit 6 AIEN
Bit 5 DIFF
Bit 4:0 ADCH
RA = 0xxx
0
1
0
00001
Read-only flag which is set when a conversion completes.
Conversion complete interrupt enabled.
Single-ended conversion selected.
Input channel 1 selected as ADC input channel.
Holds results of conversion.
CV = 0xxx
Holds compare value when compare function enabled.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
846
Freescale Semiconductor, Inc.