K60P100M100SF2RM Datasheet, PDF (7/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
4.3 Flash Memory Map.......................................................................................................................................................167
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................168
4.4 SRAM memory map.....................................................................................................................................................169
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................169
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................169
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................173
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................178
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................179
5.2 Programming model......................................................................................................................................................179
5.3 High-Level device clocking diagram............................................................................................................................179
5.4 Clock definitions...........................................................................................................................................................180
5.4.1 Device clock summary.................................................................................................................................181
5.5 Internal clocking requirements.....................................................................................................................................183
5.5.1 Clock divider values after reset....................................................................................................................184
5.5.2 VLPR mode clocking...................................................................................................................................184
5.6 Clock Gating.................................................................................................................................................................185
5.7 Module clocks...............................................................................................................................................................185
5.7.1 PMC 1-kHz LPO clock................................................................................................................................187
5.7.2 WDOG clocking..........................................................................................................................................187
5.7.3 Debug trace clock.........................................................................................................................................187
5.7.4 PORT digital filter clocking.........................................................................................................................188
5.7.5 LPTMR clocking..........................................................................................................................................188
5.7.6 Ethernet Clocking........................................................................................................................................189
5.7.7 USB FS OTG Controller clocking...............................................................................................................189
5.7.8 FlexCAN clocking.......................................................................................................................................190
5.7.9 UART clocking............................................................................................................................................190
5.7.10 SDHC clocking............................................................................................................................................191
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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