K60P100M100SF2RM Datasheet, PDF (1696/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_IER field descriptions (continued)
Field
22
RDMAE
Description
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Receive DMA Enable.
This bit allows I²S to request for DMA transfers. When enabled, DMA requests are generated when any of
the RFF0/1 bits in the ISR are set and if the corresponding RFEN bit is also set. If the corresponding FIFO
is disabled, a DMA request is generated when the corresponding RDR bit is set.
0 I²S receiver DMA requests disabled.
1 I²S receiver DMA requests enabled.
21
Receive Interrupt Enable.
RIE
This control bit allows the I²S to issue receiver related interrupts to the core.
20
TDMAE
0 I²S receiver interrupt requests disabled.
1 I²S receiver interrupt requests enabled.
Transmit DMA Enable.
This bit allows I²S to request for DMA transfers. When enabled, DMA requests are generated when any of
the ISR[TFE0/1] bits are set and if the corresponding TCR[TFEN] bit is also set. If the corresponding FIFO
is disabled, a DMA request is generated when the corresponding TDE bit is set.
0 I²S transmitter DMA requests disabled.
1 I²S transmitter DMA requests enabled.
19
Transmit Interrupt Enable.
TIE
This control bit allows the I²S to issue transmitter data related interrupts to the core.
18
CMDAUEN
0 I²S transmitter interrupt requests disabled.
1 I²S transmitter interrupt requests enabled.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
17
CMDDUEN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
16
RXTEN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
15
RDR1EN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Table continues on the next page...
1696
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.