K60P100M100SF2RM Datasheet, PDF (464/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
The state of any given channel’s interrupt request is directly affected by writes to this
register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit
position clears the corresponding channel’s interrupt request. A zero in any bit position
has no affect on the corresponding channel’s current interrupt status. The CINT register is
provided so the interrupt request for a single channel can easily be cleared without the
need to perform a read-modify-write sequence to the INT register.
Address: DMA_INT is 4000_8000h base + 24h offset = 4000_8024h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_INT field descriptions
Field
31–16
Reserved
15
INT15
14
INT14
13
INT13
12
INT12
11
INT11
Description
This read-only field is reserved and always has the value zero.
Interrupt Request 15
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
Interrupt Request 14
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
Interrupt Request 13
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
Interrupt Request 12
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
Interrupt Request 11
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
464
Freescale Semiconductor, Inc.