K60P100M100SF2RM Datasheet, PDF (1570/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Overview
• Designed to work with CE-ATA, SD memory, miniSD memory, SDIO, miniSDIO,
SD Combo, MMC, MMC plus, and MMC RS cards
• Card bus clock frequency up to 52 MHz
• Supports 1-bit / 4-bit SD and SDIO modes, 1-bit / 4-bit / 8-bit MMC modes, 1-bit /
4-bit / 8-bit CE-ATA devices
• Up to 200 Mbps of data transfer for SD/SDIO cards using 4 parallel data lines
• Up to 416 Mbps of data transfer for MMC cards using 8 parallel data lines in
SDR (single data rate) mode
• Supports single block, multi-block read and write
• Supports block sizes of 1 ~ 4096 bytes
• Supports the write protection switch for write operations
• Supports both synchronous and asynchronous abort (both hardware and software
CMD12)
• Supports pause during the data transfer at block gap
• Supports SDIO read wait and suspend resume operations
• Supports auto CMD12 for multi-block transfer
• Host can initiate non-data transfer command while data transfer is in progress
• Allows cards to interrupt the host in 1-bit and 4-bit SDIO modes, also supports
interrupt period
• Embodies a fully configurable 128x32-bit FIFO for read/write data
• Supports internal and external DMA capabilities
• Supports advanced DMA to perform linked memory access
52.2.4 Modes and operations
The SDHC can select the following modes for data transfer:
• SD 1-bit
• SD 4-bit
• MMC 1-bit
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.