K60P100M100SF2RM Datasheet, PDF (462/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
21.3.11 Clear Error Register (DMA_CERR)
The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR
to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a
global clear function, forcing the ERR contents to be cleared, clearing all channel error
indicators. If the NOP bit is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CERR is 4000_8000h base + 1Eh offset = 4000_801Eh
Bit
7
6
5
4
3
2
1
0
Read
0
0
0
Write
NOP
CAEI
0
CERR
Reset
0
0
0
0
0
0
0
0
DMA_CERR field descriptions
Field
7
NOP
6
CAEI
5–4
Reserved
3–0
CERR
Description
0 Normal operation
1 No operation, ignore the other bits in this register
Clear All Error Indicators
0 Clear only the ERR bit specified in the CERR field
1 Clear all bits in ERR
This field is reserved.
Clear Error Indicator
Clears the corresponding bit in ERR
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
462
Freescale Semiconductor, Inc.