K60P100M100SF2RM Datasheet, PDF (712/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
29.4.6 FlexBus Timing Examples
Note
The timing diagrams throughout this section use signal names
that may not be included on your particular device. Ignore these
extraneous signals.
Note
Throughout this section:
• FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus
• FB_A[Y] indicates an address bus that can be 32, 24, or 16
bits wide.
29.4.6.1 Basic Read Bus Cycle
During a read cycle, the MCU receives data from memory or a peripheral device. The
following figure shows a read cycle flowchart.
Microcontroller
System
1. Set FB_R/W to read.
2. Place address on the external address signals.
3. Assert transfer start.
1. Negate transfer start.
2. Assert FB_CSn.
1. Decode address.
1. FlexBus asserts internal FB_TA
(auto-acknowledge/internal termination).
2. Sample FB_TA low and latch data.
1. Select the appropriate slave device.
2. Drive data on the external data signals.
3. Assert FB_TA (external termination).
1. Start next cycle.
1. Negate FB_TA (external termination).
Figure 29-26. Read Cycle Flowchart
The read cycle timing diagram is shown in the following figure.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
712
Freescale Semiconductor, Inc.