K60P100M100SF2RM Datasheet, PDF (1616/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
52.4.21 ADMA System Address Register (SDHC_ADSADDR)
This register contains the physical system memory address used for ADMA transfers.
Address: SDHC_ADSADDR is 400B_1000h base + 58h offset = 400B_1058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADSADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_ADSADDR field descriptions
Field
31–2
ADSADDR
1–0
Reserved
ADMA System Address
Description
This register holds the word address of the executing command in the descriptor table. At the start of
ADMA, the host driver shall set the start address of the Descriptor table. The ADMA engine increments
this register address whenever fetching a descriptor command. When the ADMA is stopped at the block
gap, this register indicates the address of the next executable descriptor command. When the ADMA
error interrupt is generated, this register shall hold the valid descriptor address depending on the ADMA
state. The lower 2 bits of this register is tied to ‘0’ so the ADMA address is always word aligned. Since this
register supports dynamic address reflecting, when TC bit is set, it automatically alters the value of
internal address counter, so SW cannot change this register when TC bit is set.
This read-only field is reserved and always has the value zero.
52.4.22 Vendor Specific Register (SDHC_VENDOR)
This register contains the vendor specific control/status register.
Address: SDHC_VENDOR is 400B_1000h base + C0h offset = 400B_10C0h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
INTSTVAL
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1616
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.