K60P100M100SF2RM Datasheet, PDF (1124/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
Updates to the time compensation register will not take effect until the next time the time
seconds register increments and provided the previous compensation interval has expired.
When the compensation interval is set to other than once a second then the compensation
is applied in the first second interval and the remaining second intervals receive no
compensation.
Compensation is disabled by configuring the time compensation register to zero.
43.3.4 Time alarm
The time alarm register, SR[TAF] and IER[TAIE] allow the RTC to generate an interrupt
at a predefined time. The 32-bit time alarm register is compared with the 32-bit time
seconds register each time it increments. The SR[TAF] will set when the time alarm
register equals the time seconds register and the time seconds register increments.
The time alarm flag is cleared by writing the time alarm register. This will usually be the
next alarm value, although writing a value that is less than the time seconds register (such
as zero) will prevent the time alarm flag from setting again. The time alarm flag cannot
otherwise be disabled, although the interrupt it generates is enabled or disabled by
IER[TAIE].
43.3.5 Update mode
The update mode bit (CR[UM]) in the control register configures software write access to
the time counter enable (SR[TCE]) bit. When CR[UM] is clear, SR[TCE] can only be
written when the LR[SRL] bit is set. When CR[UM] is set, the SR[TCE] can also be
written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set. This allows the
time seconds and prescaler registers to be initialized whenever time is invalidated, while
preventing the time seconds and prescaler registers from being changed on the fly. When
LR[SRL] is set, the CR[UM] bit has no effect on SR[TCE].
43.3.6 Register lock
The lock register can be used to block write accesses to certain registers until the next
VBAT POR or software reset. Locking the control register will disable the software reset.
Locking the lock register will block future updates to the lock register.
Write accesses to a locked register are ignored and do not generate a bus error.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.