K60P100M100SF2RM Datasheet, PDF (976/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Definition
FTMx_CONF field descriptions (continued)
Field
4–0
NUMTOF
TOF Frequency
Description
Selects the ratio between the number of counter overflows to the number of times the TOF bit is set.
NUMTOF = 0: The TOF bit is set for each counter overflow.
NUMTOF = 1: The TOF bit is set for the first counter overflow but not for the next overflow.
NUMTOF = 2: The TOF bit is set for the first counter overflow but not for the next 2 overflows.
NUMTOF = 3: The TOF bit is set for the first counter overflow but not for the next 3 overflows.
This pattern continues up to a maximum of 31.
39.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)
This register defines the fault inputs polarity.
Addresses: FTM0_FLTPOL is 4003_8000h base + 88h offset = 4003_8088h
FTM1_FLTPOL is 4003_9000h base + 88h offset = 4003_9088h
FTM2_FLTPOL is 400B_8000h base + 88h offset = 400B_8088h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FTMx_FLTPOL field descriptions
Field
31–4
Reserved
3
FLT3POL
Description
This read-only field is reserved and always has the value zero.
Fault Input 3 Polarity
Defines the polarity of the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault input polarity is active high. A one at the fault input indicates a fault.
1 The fault input polarity is active low. A zero at the fault input indicates a fault.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
976
Freescale Semiconductor, Inc.