K60P100M100SF2RM Datasheet, PDF (921/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Trigger input event
Ch n pre-trigger 0
Ch n pre-trigger 1
... ... ... ...
Ch n pre-trigger M
Ch n trigger
Chapter 38 Programmable Delay Block (PDB)
Figure 38-54. Pre-trigger and Trigger Outputs
The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is
cleared. In this case, when the trigger input event occurs, the pre-trigger m is asserted
after two peripheral clock cycles.
The PDB can be configured in back-to-back (B2B) operation. B2B operation enables the
ADC conversions complete to trigger the next PDB channel pre-trigger and trigger
outputs, so that the ADC conversions can be triggered on next set of configuration and
results registers. When B2B is enabled by setting CHnC1[BB[m]], the delay m is ignored
and the pre-trigger m is asserted two peripheral cycles after the acknowledgment m is
received. The acknowledgment connections in this MCU is described in Back-to-back
Acknowledgement Connections.
When an ADC conversion, which is triggered by one of the pre-triggers from PDB
channel n, is in progress and ADCnSC1[COCO] is not set, a new trigger from PDB
channel n pre-trigger m cannot be accepted by ADCn. Therefore every time when one
PDB channel n pre-trigger and trigger output starts an ADC conversion, an internal lock
associated with the corresponding pre-trigger is activated. The lock becomes inactive
when the corresponding ADCnSC1[COCO] is set, or the corresponding PDB pre-trigger
is disabled, or the PDB is disabled. The channel n trigger output is suppressed when any
of the locks of the pre-triggers in channel n is active. If a new pre-trigger m asserts when
there is active lock in the PDB channel n, a register flag bit, CHnS[ERR[m]], associated
with the pre-trigger m is set. If SC[PDBEIE] is set, the sequence error interrupt is
generated. Sequence error is typically happened because the delay m is set too short and
the pre-trigger m asserts before the previous triggered ADC conversion is completed.
When the PDB counter reaches the value set in IDLY register, the SC[PDBIF] flag is set.
A PDB interrupt can be generated if SC[PDBIE] is set and SC[DMAEN] is cleared. If
SC[DMAEN] is set, PDB requests a DMA transfer when SC[PDBIF] is set.
The modulus value in MOD register, is used to reset the counter back to zero at the end
of the count. If SC[CONT] bit is set, the counter will then resume a new count.
Otherwise, the counter operation will cease until the next trigger input event occurs.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
921