K60P100M100SF2RM Datasheet, PDF (708/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
No bit ordering is required when connecting address and data lines to the FB_AD bus.
For example, a full 16-bit address/16-bit data device connects its addr[15:0] to
FB_AD[16:1] and data[15:0] to FB_AD[31:16]. See Data Byte Alignment and Physical
Connections for a graphical connection.
29.4.2 Data Transfer Operation
Data transfers between the chip and other devices involve these signals:
• Address/data bus (FB_AD[31:0])
• Control signals (FB_TS/FB_ALE, FB_TA, FB_CSn, FB_OE, FB_BEn)
• Attribute signals (FB_R/W, FB_TBST, FB_TSIZ[1:0])
The address, write data, FB_TS/FB_ALE, FB_CSn, and all attribute signals change on
the rising edge of the FlexBus clock (FB_CLK). Read data is latched into the device on
the rising edge of the clock.
The FlexBus supports 8-bit, 16-bit, 32-bit, and 16-byte (line) operand transfers and
allows accesses to 8-, 16-, and 32-bit data ports. Transfer parameters (address setup and
hold, port size, the number of wait states for the external device being accessed,
automatic internal transfer termination enable or disable, and burst enable or disable) are
programmed in the chip-select control registers (CSCRs).
29.4.3 Data Byte Alignment and Physical Connections
The device aligns data transfers in FlexBus byte lanes with the number of lanes
depending on the data port width.
The following figure shows the byte lanes that external memory connects to and the
sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is
disabled. For example, an 8-bit memory connects to the single lane FB_AD[31:24]
(FB_BE_31_24). A 32-bit transfer through this 8-bit port takes four transfers, starting
with the LSB to the MSB. A 32-bit transfer through a 32-bit port requires one transfer on
each four-byte lane of the FlexBus.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
708
Freescale Semiconductor, Inc.