K60P100M100SF2RM Datasheet, PDF (1736/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
DC[4:0]
Word Clock
Frame
Rate
Frame
Sync
TFSL
TFSI
TFDIR(1=output) _STFS
Tx
Control
Tx Frame Sync Out
TFSI
Tx Frame Sync In
TFDIR(0=input)
Figure 53-57. I²S transmit frame sync generator block diagram
53.4.2.2 DIV2, PSR and PM bits description
The bit clock frequency can be calculated from the I²S serial system clock using
id-73884.
Note
You must ensure that the bit-clock frequency must be 5 times
the peripheral clock frequency. The oversampling clock
frequency can go up to peripheral clock frequency. Bits DIV2,
PSR and PM must not be cleared at the same time.
I ²S
From this, the frame clock frequency can be calculated:
Figure 53-58. I²S bit clock equation
For example, if the I²S oversampling clock (network clock) is 12.288 MHz, in 8-bit word
normal mode with DC = 1, PM = 47, PSR = 0, DIV2 = 1, a bit clock rate of 64 kHz is
generated. Since the 8-bit word rate is equal to one (i.e. normal mode), the sampling rate
(or frame sync rate) would then be 64/(1×8) = 8 kHz.
1736
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.