K60P100M100SF2RM Datasheet, PDF (919/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
15–0
INT
Chapter 38 Programmable Delay Block (PDB)
PDBx_DACINTn field descriptions (continued)
DAC Interval
Description
These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update
when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal
register that is effective for the current PDB cycle.
38.3.11 Pulse-Out n Enable Register (PDBx_POEN)
Addresses: PDB0_PO0EN is 4003_6000h base + 190h offset = 4003_6190h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
POEN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnEN field descriptions
Field
31–8
Reserved
7–0
POEN
Description
This read-only field is reserved and always has the value zero.
PDB Pulse-Out Enable
These bits enable the pulse output. Only lower Y bits are implemented in this MCU.
0 PDB Pulse-Out disabled
1 PDB Pulse-Out enabled
38.3.12 Pulse-Out n Delay Register (PDBx_PODLY)
Addresses: PDB0_PO0DLY is 4003_6000h base + 194h offset = 4003_6194h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLY1
W
DLY2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnDLY field descriptions
Field
31–16
DLY1
PDB Pulse-Out Delay 1
Description
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
919