K60P100M100SF2RM Datasheet, PDF (1068/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Description
40.3.4 Timer Control Register (PIT_TCTRLn)
These register contain the control bits for each timer.
Addresses: PIT_TCTRL0 is 4003_7000h base + 108h offset = 4003_7108h
PIT_TCTRL1 is 4003_7000h base + 118h offset = 4003_7118h
PIT_TCTRL2 is 4003_7000h base + 128h offset = 4003_7128h
PIT_TCTRL3 is 4003_7000h base + 138h offset = 4003_7138h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_TCTRLn field descriptions
Field
31–2
Reserved
1
TIE
Description
This read-only field is reserved and always has the value zero.
Timer Interrupt Enable Bit.
When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt event. To
avoid this, the associated TIF flag must be cleared first.
0
TEN
0 Interrupt requests from Timer n are disabled.
1 Interrupt will be requested whenever TIF is set.
Timer Enable Bit.
This bit enables or disables the timer.
0 Timer n is disabled.
1 Timer n is active.
40.3.5 Timer Flag Register (PIT_TFLGn)
These registers hold the PIT interrupt flags.
Addresses: PIT_TFLG0 is 4003_7000h base + 10Ch offset = 4003_710Ch
PIT_TFLG1 is 4003_7000h base + 11Ch offset = 4003_711Ch
PIT_TFLG2 is 4003_7000h base + 12Ch offset = 4003_712Ch
PIT_TFLG3 is 4003_7000h base + 13Ch offset = 4003_713Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1068
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.