K60P100M100SF2RM Datasheet, PDF (860/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definitions
• If enabled, the Filter Block will incur up to 1 bus clock additional latency penalty on
COUT due to the fact that COUT (which is crossing clock domain boundaries) must
be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
35.7 Memory Map/Register Definitions
Absolute
address
(hex)
CMP memory map
Register name
Width
(in bits)
Access
Reset value
4007_3000 CMP Control Register 0 (CMP0_CR0)
8
R/W
00h
4007_3001 CMP Control Register 1 (CMP0_CR1)
8
R/W
00h
4007_3002 CMP Filter Period Register (CMP0_FPR)
8
R/W
00h
4007_3003 CMP Status and Control Register (CMP0_SCR)
8
R/W
00h
4007_3004 DAC Control Register (CMP0_DACCR)
8
R/W
00h
4007_3005 MUX Control Register (CMP0_MUXCR)
8
R/W
00h
4007_3008 CMP Control Register 0 (CMP1_CR0)
8
R/W
00h
4007_3009 CMP Control Register 1 (CMP1_CR1)
8
R/W
00h
4007_300A CMP Filter Period Register (CMP1_FPR)
8
R/W
00h
4007_300B CMP Status and Control Register (CMP1_SCR)
8
R/W
00h
4007_300C DAC Control Register (CMP1_DACCR)
8
R/W
00h
4007_300D MUX Control Register (CMP1_MUXCR)
8
R/W
00h
4007_3010 CMP Control Register 0 (CMP2_CR0)
8
R/W
00h
4007_3011 CMP Control Register 1 (CMP2_CR1)
8
R/W
00h
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
860
Freescale Semiconductor, Inc.