K60P100M100SF2RM Datasheet, PDF (1572/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
Table 52-1. SDHC signal descriptions (continued)
SDHC_D6
Signal
SDHC_D7
Description
I/O
DAT6 line in 8-bit mode
I/O
Not used in other modes
DAT7 line in 8-bit mode
I/O
Not used in other modes
52.4 Memory map and register definition
This section includes the module memory map and detailed descriptions of all registers.
Absolute
address
(hex)
SDHC memory map
Register name
Width
(in bits)
Access
Reset value
400B_1000 DMA System Address Register (SDHC_DSADDR)
32
R/W 0000_0000h
400B_1004 Block Attributes Register (SDHC_BLKATTR)
32
R/W 0000_0000h
400B_1008 Command Argument Register (SDHC_CMDARG)
32
R/W 0000_0000h
400B_100C Transfer Type Register (SDHC_XFERTYP)
32
R/W 0000_0000h
400B_1010 Command Response 0 (SDHC_CMDRSP0)
32
R
0000_0000h
400B_1014 Command Response 1 (SDHC_CMDRSP1)
32
R
0000_0000h
400B_1018 Command Response 2 (SDHC_CMDRSP2)
32
R
0000_0000h
400B_101C Command Response 3 (SDHC_CMDRSP3)
32
R
0000_0000h
400B_1020 Buffer Data Port Register (SDHC_DATPORT)
32
R/W 0000_0000h
400B_1024 Present State Register (SDHC_PRSSTAT)
32
R
0000_0000h
400B_1028 Protocol Control Register (SDHC_PROCTL)
32
R/W 0000_0020h
400B_102C System Control Register (SDHC_SYSCTL)
32
Table continues on the next page...
R/W 0000_8008h
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.