K60P100M100SF2RM Datasheet, PDF (1112/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register definition
RTC_TSR field descriptions
Field
31–0
TSR
Time Seconds Register
Description
When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF]
or SR[TIF] are not set. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the
time counter is disabled, the TSR can be read or written. Writing to the TSR when the time counter is
disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to the TSR register with zero is supported, but
not recommended since TSR will read as zero when SR[TIF] or SR[TOF] are set (indicating the time is
invalid).
43.2.2 RTC Time Prescaler Register (RTC_TPR)
Address: RTC_TPR is 4003_D000h base + 4h offset = 4003_D004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
TPR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_TPR field descriptions
Field
31–16
Reserved
15–0
TPR
Description
This read-only field is reserved and always has the value zero.
Time Prescaler Register
When the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle.
The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled,
the TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic
one to a logic zero.
43.2.3 RTC Time Alarm Register (RTC_TAR)
Address: RTC_TAR is 4003_D000h base + 8h offset = 4003_D008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_TAR field descriptions
Field
31–0
TAR
Time Alarm Register
Description
1112
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.