K60P100M100SF2RM Datasheet, PDF (1154/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
ENET_IAUR field descriptions
Field
31–0
IADDR1
Description
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with
a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit
32.
44.3.15 Descriptor Individual Lower Address Register (ENET_IALR)
IALR contains the lower 32 bits of the 64-bit individual address hash table. The address
recognition process uses this table to check for a possible match with the DA field of
receive frames with an individual DA. This register is not reset and you must initialize it.
Address: ENET_IALR is 400C_0000h base + 11Ch offset = 400C_011Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IADDR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IALR field descriptions
Field
31–0
IADDR2
Description
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with
a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit
0.
44.3.16 Descriptor Group Upper Address Register (ENET_GAUR)
GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. You must initialize this register.
Address: ENET_GAUR is 400C_0000h base + 120h offset = 400C_0120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GADDR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_GAUR field descriptions
Field
31–0
GADDR1
Description
Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains
hash index bit 32.
1154
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.