K60P100M100SF2RM Datasheet, PDF (1145/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Address: ENET_MMFR is 400C_0000h base + 40h offset = 400C_0040h
Chapter 44 10/100-Mbps Ethernet MAC (ENET)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ST OP
PA
W
RA
TA
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_MMFR field descriptions
Field
31–30
ST
29–28
OP
Start of frame delimiter
Description
These bits must be programmed to 01 for a valid MII management frame.
Operation code
Determines the frame operation.
27–23
PA
22–18
RA
17–16
TA
15–0
DATA
00 Write frame operation, but not MII compliant.
01 Write frame operation for a valid MII management frame.
10 Read frame operation for a valid MII management frame.
11 Read frame operation, but not MII compliant.
PHY address
PHY address. Specifies one of up to 32 attached PHY devices.
Register address
Specifies one of up to 32 registers within the specified PHY device.
Turn around
This field must be programmed to 10 to generate a valid MII management frame.
Management frame data
This is the field for data to be written to or read from the PHY register.
44.3.7 MII Speed Control Register (ENET_MSCR)
MSCR provides control of the MII clock (MDC pin) frequency and allows a preamble
drop on the MII management frame.
The MII_SPEED field must be programmed with a value to provide an MDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification.
The MII_SPEED must be set to a non-zero value to source a read or write management
frame. After the management frame is complete, the MSCR register may optionally be
cleared to turn off MDC. The MDC signal generated has a 50% duty cycle except when
MII_SPEED changes during operation (change takes effect following a rising or falling
edge of MDC).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1145