K60P100M100SF2RM Datasheet, PDF (946/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Definition
FTMx_CnSC field descriptions (continued)
Field
4
MSA
3
ELSB
2
ELSA
1
Reserved
0
DMA
Description
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
Table 39-7.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. See Table 39-7.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. See Table 39-7.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
This read-only field is reserved and always has the value zero.
DMA Enable
Enables DMA transfers for the channel.
0 Disable DMA transfers.
1 Enable DMA transfers.
39.3.7 Channel (n) Value (FTMx_CV)
These registers contain the captured FTM counter value for the input modes or the match
value for the output modes.
In input capture, capture test, and dual edge capture modes, any write to a CnV register is
ignored.
In output modes, writing to a CnV register latches the value into a buffer. A CnV register
is updated with the value of its write buffer according to Registers Updated from Write
Buffers.
If FTMEN = 0, this write coherency mechanism may be manually reset by writing to the
CnSC register (whether BDM mode is active or not).
Addresses: FTM0_C0V is 4003_8000h base + 10h offset = 4003_8010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
VAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
946
Freescale Semiconductor, Inc.