K60P100M100SF2RM Datasheet, PDF (1511/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
7
TXEMPT
6
RXEMPT
5–2
Reserved
1
TXOF
0
RXUF
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_SFIFO field descriptions
Transmit Buffer/FIFO Empty
Description
This status bit asserts when there is no data in the Transmit FIFO/buffer. This bit does not take into
account data that is in the transmit shift register.
0 Transmit buffer is not empty.
1 Transmit buffer is empty.
Receive Buffer/FIFO Empty
This status bit asserts when there is no data in the receive FIFO/Buffer. This bit does not take into
account data that is in the receive shift register.
0 Receive buffer is not empty.
1 Receive buffer is empty.
This read-only field is reserved and always has the value zero.
Transmitter Buffer Overflow Flag
This flag indicates that more data has been written to the transmit buffer than it can hold. This bit will
assert regardless of the value of CFIFO[TXOFE]. However, an interrupt will only be issued to the host if
the CFIFO[TXOFE] bit is set. This flag is cleared by writing a "1".
0 No transmit buffer overflow has occurred since the last time the flag was cleared.
1 At least one transmit buffer overflow has occurred since the last time the flag was cleared.
Receiver Buffer Underflow Flag
This flag indicates that more data has been read from the receive buffer than was present. This bit will
assert regardless of the value of CFIFO[RXUFE]. However, an interrupt will only be issued to the host if
the CFIFO[RXUFE] bit is set. This flag is cleared by writing a "1".
0 No receive buffer underflow has occurred since the last time the flag was cleared.
1 At least one receive buffer underflow has occurred since the last time the flag was cleared.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1511