K60P100M100SF2RM Datasheet, PDF (809/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
Chapter 34 Analog-to-Digital Converter (ADC)
ADCx_SC1n field descriptions (continued)
10111
11000
11001
11010
11011
11100
11101
11110
11111
Description
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
Reserved.
Reserved.
When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor
(differential) is selected as input.
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap
(differential) is selected as input.
Reserved.
When DIFF=0, V_REFSH is selected as input; when DIFF=1, -V_REFSH (differential) is selected as
input. Voltage reference selected is determined by the REFSEL bits in the SC2 register.
When DIFF=0, V_REFSL is selected as input; when DIFF=1, it is reserved. Voltage reference
selected is determined by the REFSEL bits in the SC2 register.
Module disabled.
34.3.2 ADC configuration register 1 (ADCx_CFG1)
CFG1 register selects the mode of operation, clock source, clock divide, and configure
for low power or long sample time.
Addresses: ADC0_CFG1 is 4003_B000h base + 8h offset = 4003_B008h
ADC1_CFG1 is 400B_B000h base + 8h offset = 400B_B008h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
ADIV
MODE
ADICLK
Reset 0
Field
31–8
Reserved
7
ADLPC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCx_CFG1 field descriptions
Description
This read-only field is reserved and always has the value zero.
Low-power configuration
ADLPC controls the power configuration of the successive approximation converter. This optimizes power
consumption when higher sample rates are not required.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
809