K60P100M100SF2RM Datasheet, PDF (243/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chip signal name
DAC0_OUT
Chip signal name
TRI1_DP
TRI1_DM
TRI1_OUT
Chip signal name
VREF_OUT
Chapter 10 Signal Multiplexing and Signal Descriptions
Table 10-16. DAC 0 Signal Descriptions
Module signal Description
I/O
name
—
DAC output
O
Table 10-17. TRIAMP 1 Signal Descriptions
Module signal Description
I/O
name
inp_3v
Amplifier positive input terminal
I
inn_3v
Amplifier negative input terminal
I
out_3v
Amplifier output terminal
O
Table 10-18. VREF Signal Descriptions
Module signal Description
I/O
name
VREF_OUT
Internally-generated Voltage Reference output
O
10.4.6 Communication Interfaces
Ethernet MII Signal Descriptions
Chip signal name
MII0_COL
MII0_CRS
MII0_MDC
MII0_MDIO
Module signal name
MII_COL
MII_CRS
Description
I/O
Asserted upon detection of a I
collision and remains
asserted while the collision
persists. This signal is not
defined for full-duplex mode.
Carrier sense. When
I
asserted, indicates transmit
or receive medium is not idle.
MII_MDC
MII_MDIO
In RMII mode, this signal is
present on the
RMII_CRS_DV pin.
Output clock provides a
O
timing reference to the PHY
for data transfers on the
MDIO signal.
Transfers control information I/O
between the external PHY
and the media-access
controller. Data is
synchronous to MDC. This
signal is an input after reset.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
243