K60P100M100SF2RM Datasheet, PDF (112/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memories and Memory Interfaces
Transfers
Peripheral
bridge 0
Register
access
FlexBus
Module signals
Figure 3-31. FlexBus configuration
Table 3-42. Reference links to related information
Topic
Full description
System memory map
Clocking
Power management
Transfers
Signal multiplexing
Related module
FlexBus
Memory protection unit
(MPU)
Port control
Reference
FlexBus
System memory map
Clock distribution
Power management
Memory protection unit (MPU)
Signal multiplexing
3.5.8.1 FlexBus clocking
The system provides a dedicated clock source to the FlexBus module's external
FB_CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See
Clock Distribution for more details.
3.5.8.2 FlexBus signal multiplexing
The multiplexing of the FlexBus address and data signals is controlled by the port control
module. However, the multiplexing of some of the FlexBus control signals are controlled
by the port control and FlexBus modules. The port control module registers control
whether the FlexBus or another module signals are available on the external pin, while
the FlexBus's CSPMCR register configures which FlexBus signals are available from the
module. The control signals are grouped as illustrated:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
112
Freescale Semiconductor, Inc.