K60P100M100SF2RM Datasheet, PDF (549/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_C6 field descriptions (continued)
Description
Table 24-9. PLL VCO Divide Factor (continued)
00001 25
00010 26
00011 27
00100 28
00101 29
00110 30
00111 31
01001 33
01010 34
01011 35
01100 36
01101 37
01110 38
01111 39
10001 41
10010 42
10011 43
10100 44
10101 45
10110 46
10111 47
11001 49
11010 50
11011 51
11100 52
11101 53
11110 54
11111 55
24.3.7 MCG Status Register (MCG_S)
Address: MCG_S is 4006_4000h base + 6h offset = 4006_4006h
Bit
7
6
5
4
Read
LOLS
LOCK
PLLST
IREFST
3
2
CLKST
1
0
IRCST
Write
Reset
Field
7
LOLS
6
LOCK
0
0
0
1
0
0
0
0
MCG_S field descriptions
Loss of Lock Status
Description
This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL
output frequency has fallen outside the lock exit frequency tolerance, D _unl . LOLIE determines whether an
interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when
LOLS0 is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit
has no effect.
0 PLL has not lost lock since LOLS was last cleared.
1 PLL has lost lock since LOLS was last cleared.
Lock Status
This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in
either PBE or PEE mode unless PLLCLKEN =1 and the MCG is not configured in BLPI or BLPE mode.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
549