K60P100M100SF2RM Datasheet, PDF (1227/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
A complete frame has a length of 64 bits (optional 32-bit preamble, 14-bit command, 2-
bit bus direction change, 16-bit data). Each bit is transferred on the rising edge of the
MDIO clock (MDC signal).
The core PHY management interface supports the standard MDIO specification
(IEEE803.2 Clause 22).
Table 44-91. MDIO Frame Formats (Read/Write)
Type
Read
Write
PRE
1…1
1…1
Command
ST
OP
Addr1
Addr2
01
10
xxxxx
xxxxx
01
01
xxxxx
xxxxx
Data
TA
MSB
Idle
LSB
Z0
xxxxxxxxxxxxxxxx
Z
10
xxxxxxxxxxxxxxxx
Z
Field
PRE
ST
OP
Addr1
Addr2
TA
Data
Idle
Table 44-92. MDIO Frame Field Descriptions
Description
Preamble. 32 bits of logical ones sent prior to every transaction when ENETn_MSCR[DIS_PRE] is
cleared. If DIS_PRE is set, the preamble is not generated.
Start indication, programmed with ENETn_MMFR[ST]
• Standard MDIO (Clause 22): 01
Opcode defines if a read or write operation is performed, programmed with ENETn_MMFR[OP].
01 Write operation
10 Read operation
The PHY device address, programmed with ENETn_MMFR[PA]. Up to 32 devices can be
addressed.
Register address, programmed with ENETn_MMFR[RA]. Each PHY can implement up to 32
registers.
Turnaround time, programmed with ENETn_MMFR[TA]. Two bit-times are reserved for read
operations to switch the data bus from write to read for read operations. The PHY device presents
its register contents in the data phase and drives the bus from the second bit of the turnaround
phase.
16 bits of data, set to ENETn_MMFR[DATA], written to or read from the PHY
Between frames the MDIO data signal is tri-stated.
44.4.17.2 MDIO Clock Generation
The MDC clock is generated from the internal bus clock divided by the value
programmed in ENETn_MSCR[MII_SPEED].
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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