K60P100M100SF2RM Datasheet, PDF (1396/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
49.3 Memory Map/Register Definition
Register accesses to memory addresses that are reserved or undefined result in a transfer
error. Write access to the POPR register also results in a transfer error.
Absolute
address
(hex)
SPI memory map
Register name
Width
(in bits)
Access
Reset value
4002_C000 DSPI Module Configuration Register (SPI0_MCR)
32
R/W 0000_4001h
4002_C008 DSPI Transfer Count Register (SPI0_TCR)
4002_C00C
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI0_CTAR0)
4002_C00C
DSPI Clock and Transfer Attributes Register (In Slave
Mode) (SPI0_CTAR0_SLAVE)
4002_C010
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI0_CTAR1)
4002_C02C DSPI Status Register (SPI0_SR)
4002_C030
DSPI DMA/Interrupt Request Select and Enable Register
(SPI0_RSER)
4002_C034
DSPI PUSH TX FIFO Register In Master Mode
(SPI0_PUSHR)
4002_C034
DSPI PUSH TX FIFO Register In Slave Mode
(SPI0_PUSHR_SLAVE)
4002_C038 DSPI POP RX FIFO Register (SPI0_POPR)
32
R/W 0000_0000h
32
R/W 7800_0000h
32
R/W 7800_0000h
32
R/W 7800_0000h
32
R/W See section
32
R/W 0000_0000h
32
R/W 0000_0000h
32
R/W 0000_0000h
32
R
0000_0000h
4002_C03C DSPI Transmit FIFO Registers (SPI0_TXFR0)
32
R
0000_0000h
4002_C040 DSPI Transmit FIFO Registers (SPI0_TXFR1)
32
R
0000_0000h
4002_C044 DSPI Transmit FIFO Registers (SPI0_TXFR2)
32
R
0000_0000h
4002_C048 DSPI Transmit FIFO Registers (SPI0_TXFR3)
32
R
0000_0000h
4002_C07C DSPI Receive FIFO Registers (SPI0_RXFR0)
32
R
0000_0000h
4002_C080 DSPI Receive FIFO Registers (SPI0_RXFR1)
32
Table continues on the next page...
R
0000_0000h
Section/
page
49.3.1/
1399
49.3.2/
1402
49.3.3/
1402
49.3.4/
1407
49.3.3/
1402
49.3.5/
1408
49.3.6/
1411
49.3.7/
1413
49.3.8/
1415
49.3.9/
1415
49.3.10/
1416
49.3.10/
1416
49.3.10/
1416
49.3.10/
1416
49.3.11/
1416
49.3.11/
1416
1396
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.