K60P100M100SF2RM Datasheet, PDF (224/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Debug Resets
Table 9-6. MDM-AP Status register assignments (continued)
Bit
Name
7
LP Enabled
8
Very Low Power Mode
9
LLS Mode Exit
10
VLLSx Modes Exit
11 – 15
16
17
18
Reserved for future use
Core Halted
Core SLEEPDEEP
Core SLEEPING
19 – 31 Reserved for future use
Description
Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are
the selected power mode the next time the ARM Core enters Deep Sleep.
0 Low Power Stop Mode is not enabled
1 Low Power Stop Mode is enabled
Usage intended for debug operation in which Run to VLPS is attempted.
Per debug definition, the system actually enters the Stop state. A
debugger should interpret deep sleep indication (with SLEEPDEEP and
SLEEPING asserted), in conjuntion with this bit asserted as the debugger-
VLPS status indication.
Indicates current power mode is VLPx. This bit is not ‘sticky’ and should
always represent whether VLPx is enabled or not.
This bit is used to throttle JTAG TCK frequency up/down.
This bit indicates an exit from LLS mode has occurred. The debugger will
lose communication while the system is in LLS (including access to this
register). Once communication is reestablished, this bit indicates that the
system had been in LLS. Since the debug modules held their state during
LLS, they do not need to be reconfigured.
This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is
held until the debugger has had a chance to recognize that LLS was
exited and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
This bit indicates an exit from VLLSx mode has occurred. The debugger
will lose communication while the system is in VLLSx (including access to
this register). Once communication is reestablished, this bit indicates that
the system had been in VLLSx. Since the debug modules lose their state
during VLLSx modes, they need to be reconfigured.
This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit
bit is held until the debugger has had a chance to recognize that a VLLS
mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
Always read 0.
Indicates the Core has entered debug halt mode
Indicates the Core has entered a low power mode
SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode.
SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode.
Always read 0.
9.6 Debug Resets
The debug system receives the following sources of reset:
• JTAG_TRST_b from an external signal. This signal is optional and may not be
available in all packages.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
224
Freescale Semiconductor, Inc.