K60P100M100SF2RM Datasheet, PDF (88/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

System modules
3.3.7.2 MPU Logical Bus Master Assignments
The logical bus master assignments for the MPU are:
Table 3-18. MPU Logical Bus Master Assignments
MPU Logical Bus Master Number
0
1
2
3
4
5
6
7
Core
Debugger
DMA
ENET
USB
SDHC
none
none
Bus Master
3.3.7.3 MPU Access Violation Indications
Access violations detected by the MPU are signaled to the appropriate bus master as
shown below:
Table 3-19. Access Violation Indications
Core
Bus Master
Debugger
DMA
Ethernet
USB_OTG
SDHC
Core Indication
Bus fault (interrupt vector #5) Note: To enable bus faults set the core's System
Handler Control and State Register's BUSFAULTENA bit. If this bit is not set, MPU
violations result in a hard fault (interrupt vector #3).
The STICKYERROR flag is set in the Debug Port Control/Status Register.
Interrupt vector #32
Interrupt vector #94
Interrupt vector #89
Interrupt vector #96
3.3.7.4 Reset Values for RGD0 Registers
At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire
4 GB address space with read, write and execute permissions given to the core, debugger
and the DMA bus masters.
The following table shows the chip-specific reset values for RGD0 and RGDAAC0.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
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Freescale Semiconductor, Inc.