K60P100M100SF2RM Datasheet, PDF (456/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
DMA_EEI field descriptions (continued)
Field
1
EEI1
0
EEI0
Description
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Enable Error Interrupt 1
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Enable Error Interrupt 0
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte
registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CEEI is 4000_8000h base + 18h offset = 4000_8018h
Bit
7
6
5
4
3
2
1
0
Read
0
0
0
Write
NOP
CAEE
0
CEEI
Reset
0
0
0
0
0
0
0
0
DMA_CEEI field descriptions
Field
7
NOP
6
CAEE
5–4
Reserved
3–0
CEEI
Description
0 Normal operation
1 No operation, ignore the other bits in this register
Clear All Enable Error Interrupts
0 Clear only the EEI bit specified in the CEEI field
1 Clear all bits in EEI
This field is reserved.
Clear Enable Error Interrupt
Clears the corresponding bit in EEI
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
456
Freescale Semiconductor, Inc.