K60P100M100SF2RM Datasheet, PDF (1306/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
Peripheral Bus Interface
Address, Data, Clocks, Interrupts
Registers
CAN Control
Host Interface
Tx
Arbitration
Rx
Matching
Message
Buffers
(MBs)
RAM
CAN Protocol Engine
CAN Tx
CAN Rx
CAN Bus
Figure 48-1. FlexCAN Block Diagram
Chip
48.1.1 Overview
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial
data bus, meeting the specific requirements of this field: real-time processing, reliable
operation in the EMI environment of a vehicle, cost-effectiveness and required
bandwidth. The FlexCAN module is a full implementation of the CAN protocol
specification, Version 2.0 B, which supports both standard and extended message frames.
The Message Buffers are stored in an embedded RAM dedicated to the FlexCAN
module. See the Chip Configuration details for the actual number of Message Buffers
configured in the MCU.
The CAN Protocol Engine (PE) sub-module manages the serial communication on the
CAN bus, requesting RAM access for receiving and transmitting message frames,
validating received messages and performing error handling. The Controller Host
Interface (CHI) sub-module handles Message Buffer selection for reception and
transmission, taking care of arbitration and ID matching algorithms. The Bus Interface
Unit (BIU) sub-module controls the access to and from the internal interface bus, in order
to establish connection to the CPU and to other blocks. Clocks, address and data buses,
interrupt outputs and test signals are accessed through the Bus Interface Unit.
1306
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.