K60P100M100SF2RM Datasheet, PDF (800/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
• Input clock selectable from up to four sources
• Operation in low power modes for lower noise operation
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable hardware conversion trigger with hardware channel select
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable voltage reference: external or alternate
• Self-calibration mode
• Programmable Gain Amplifier (PGA) with up to x64 gain
34.1.2 Block diagram
The following figure is the ADC module block diagram.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
800
Freescale Semiconductor, Inc.