K60P100M100SF2RM Datasheet, PDF (1146/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
If the internal module clock is 25 MHz, programming this register to 0x0000_0004
results in an MDC as stated the equation below.
25 MHz / ((4 + 1) x 2) = 2.5 MHz
The following table shows the optimum values for MII_SPEED as a function of internal
module clock frequency.
Table 44-10. Programming Examples for MSCR
Internal MAC clock frequency
MSCR [MII_SPEED]
25 MHz
0x4
33 MHz
0x6
40 MHz
0x7
50 MHz
0x9
66 MHz
0xD
MDC frequency
2.50 MHz
2.36 MHz
2.50 MHz
2.50 MHz
2.36 MHz
Address: ENET_MSCR is 400C_0000h base + 44h offset = 400C_0044h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
HOLDTIME
0
MII_SPEED
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENET_MSCR field descriptions
Field
31–11
Reserved
10–8
HOLDTIME
Description
This read-only field is reserved and always has the value zero.
Holdtime on MDIO output
IEEE802.3 clause 22 defines a minimum of 10 ns for the holdtime on the MDIO output. Depending on the
host bus frequency the setting may need to be increased.
7
DIS_PRE
000 1 internal module clock cycle
001 2 internal module clock cycles
010 3 internal module clock cycles
111 8 internal module clock cycles
Disable preamble
Table continues on the next page...
1146
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.