K60P100M100SF2RM Datasheet, PDF (774/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
Value of bits 31, 20, and 9
100
110
111
Number of commands included
1
2
3
All other combinations of bits 31, 20, and 9 are illegal and generate an error termination.
32.6.3 CAU Commands
The CAU supports the commands shown in the following table. All other encodings are
reserved. The CASR[IC] bit is set if an undefined command is issued. A specific illegal
command (ILL) is defined to allow software self-checking. Reserved commands should
not be issued to ensure compatibility with future implementations.
The CMD field specifies the 9-bit CAU opcode for the operation command.
See Assembler Equate Values for a set of assembly constants used in the command
descriptions here. If supported by the assembler, macros can also be created for each
instruction. The value CAx should be interpreted as any CAU register (CASR, CAA,
CAn).
Type
Direct load
Indirect load
Indirect store
Indirect load
Indirect load
Direct load
Indirect load
Indirect load
Direct load
Direct load
Direct load
Direct load
Indirect load
Command
Name
CNOP
LDR
STR
ADR
RADR
ADRA
XOR
ROTL
MVRA
MVAR
AESS
AESIS
AESC
Table 32-15. CAU Commands
Description
No Operation
CMD
87654321
0x000
Load Reg
0x01
CAx
Store Reg
0x02
CAx
Add
0x03
CAx
Reverse and Add
0x04
CAx
Add Reg to Acc
0x05
CAx
Exclusive Or
0x06
CAx
Rotate Left
0x07
CAx
Move Reg to Acc
0x08
CAx
Move Acc to Reg
0x09
CAx
AES Sub Bytes
0x0A
CAx
AES Inv Sub Bytes
0x0B
CAx
AES Column Op
0x0C
CAx
Table continues on the next page...
Operation
0
—
Op1 → CAx
CAx → Result
CAx + Op1 → CAx
CAx + ByteRev(Op1) → CAx
CAx + CAA → CAA
CAx ^ Op1 → CAx
(CAx <<< (Op1 % 32)) |
(CAx >>> (32 - (Op1 % 32)))
→ CAx
CAx → CAA
CAA → CAx
SubBytes(CAx) → CAx
InvSubBytes(CAx) → CAx
MixColumns(CAx)^Op1→
CAx
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
774
Freescale Semiconductor, Inc.