K60P100M100SF2RM Datasheet, PDF (918/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Definition
38.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn)
Addresses: PDB0_DACINTC0 is 4003_6000h base + 150h offset = 4003_6150h
PDB0_DACINTC1 is 4003_6000h base + 158h offset = 4003_6158h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_DACINTCn field descriptions
Field
31–2
Reserved
1
EXT
Description
This read-only field is reserved and always has the value zero.
DAC External Trigger Input Enable
This bit enables the external trigger for DAC interval counter.
0
TOE
0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising
edge is detected on selected trigger input source or software trigger is selected and SWTRIG is
written with 1.
1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input
triggers the DAC interval trigger.
DAC Interval Trigger Enable
This bit enables the DAC interval trigger.
0 DAC interval trigger disabled.
1 DAC interval trigger enabled.
38.3.10 DAC Interval n Register (PDBx_DACINTn)
Addresses: PDB0_DACINT0 is 4003_6000h base + 154h offset = 4003_6154h
PDB0_DACINT1 is 4003_6000h base + 15Ch offset = 4003_615Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_DACINTn field descriptions
Field
31–16
Reserved
Description
This read-only field is reserved and always has the value zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
918
Freescale Semiconductor, Inc.