K60P100M100SF2RM Datasheet, PDF (434/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
• The first region defines a number of registers providing control functions
• The second region corresponds to the local transfer control descriptor memory
Each channel requires a 32-byte transfer control descriptor for defining the desired data
movement operation. The channel descriptors are stored in the local memory in
sequential order: channel 0, channel 1,... channel 15 . Each TCDn definition is presented
as 11 registers of 16 or 32 bits.
Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a
register are ignored. Reading or writing a reserved memory location generates a bus
error.
DMA memory map
Absolute
address
(hex)
Register name
4000_8000 Control Register (DMA_CR)
4000_8004 Error Status Register (DMA_ES)
4000_800C Enable Request Register (DMA_ERQ)
4000_8014 Enable Error Interrupt Register (DMA_EEI)
4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI)
4000_8019 Set Enable Error Interrupt Register (DMA_SEEI)
4000_801A Clear Enable Request Register (DMA_CERQ)
4000_801B Set Enable Request Register (DMA_SERQ)
4000_801C Clear DONE Status Bit Register (DMA_CDNE)
4000_801D Set START Bit Register (DMA_SSRT)
Width
(in bits)
Access
Reset value
Section/
page
32
R/W 0000_0000h 21.3.1/448
32
R
0000_0000h 21.3.2/450
32
R/W 0000_0000h 21.3.3/452
32
R/W 0000_0000h 21.3.4/454
W
8
(always
reads
00h
zero)
21.3.5/456
W
8
(always
reads
00h
zero)
21.3.6/457
W
8
(always
reads
00h
zero)
21.3.7/458
W
8
(always
reads
00h
zero)
21.3.8/459
W
8
(always
reads
00h
zero)
21.3.9/460
W
8
(always
reads
00h
zero)
21.3.10/
461
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
434
Freescale Semiconductor, Inc.