K60P100M100SF2RM Datasheet, PDF (97/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
3.3.12.1 WDOG clocks
This table shows the WDOG module clocks and the corresponding chip clocks.
Table 3-30. WDOG clock connections
LPO Oscillator
Alt Clock
Fast Test Clock
System Bus Clock
Module clock
1 kHz LPO Clock
Bus Clock
Bus Clock
Bus Clock
Chip clock
3.3.12.2 WDOG low-power modes
This table shows the WDOG low-power modes and the corresponding chip low-power
modes.
Table 3-31. WDOG low-power modes
Wait
Standby
Stop
Power Down
Module mode
Wait, VLPW
Stop, VLPS
Stop, VLPS
LLS, VLLSx
Chip mode
NOTE
To enable the WDOG module when the chip is in Stop mode,
write ones to both the STNDBYEN bit and the STOPEN bit of
the Watchdog Status and Control Register High.
3.4 Clock Modules
3.4.1 MCG Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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