K60P100M100SF2RM Datasheet, PDF (91/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

3.3.8.5 PACR registers
Chapter 3 Chip Configuration
Each of the two peripheral bridges support up to 128 peripherals each assigned to an
PACRx field within the PACRA-PACRP registers. However, fewer peripherals are
supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of
the peripheral slot assignments for this device. Unused PACRx fields are reserved.
3.3.8.6 AIPS_Lite PACRE-P register reset values
The AIPSx_PACRE-P reset values depend on if the module is available on your
particular device. For each populated slot in slots 32-127 in Peripheral Bridge 0 (AIPS-
Lite 0) Memory Map and Peripheral Bridge 1 (AIPS-Lite 1) Memory Map, the
corresponding module's PACR[32:127] field resets to 0x4.
3.3.9 DMA request multiplexer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge 0
Register
access
Channel
request
DMA Request
Multiplexer
Requests
Module
Module
Module
Figure 3-13. DMA request multiplexer configuration
Table 3-23. Reference links to related information
Topic
Full description
System memory map
Clocking
Power management
Channel request
Requests
Related module
DMA request
multiplexer
DMA controller
Reference
DMA Mux
System memory map
Clock distribution
Power management
DMA Controller
DMA request sources
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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