K60P100M100SF2RM Datasheet, PDF (1386/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/Application Information
• Write access to positions whose bits are all currently read-only results in access error.
If at least one of the bits is not read-only then no access error is issued. Write
permission to positions or some of their bits can change depending on the mode of
operation or transitory state. Refer to register and bit descriptions for details.
• Read and write access to unimplemented address space results in access error.
• Read and write access to RAM located positions during Low Power Mode results in
access error.
• If MAXMB is programmed with a value smaller than the available number of MBs,
then the unused memory space can be used as general purpose RAM space. Note that
reserved words within RAM cannot be used. As an example, suppose FlexCAN is
configured with 16 MBs, RFFN is 0x0, and MAXMB is programmed with zero. The
maximum number of MBs in this case becomes one. The RAM starts at 0x0080, and
the space from 0x0080 to 0x008F is used by the one MB. The memory space from
0x0090 to 0x017F is available. The space between 0x0180 and 0x087F is reserved.
The space from 0x0880 to 0x0883 is used by the one Individual Mask and the
available memory in the Mask Registers space would be from 0x0884 to 0x08BF.
From 0x08C0 through 0x09DF there are reserved words for internal use which
cannot be used as general purpose RAM. As a general rule, free memory space for
general purpose depends only on MAXMB.
Note
Unused MB space must not be used as general purpose RAM
while FlexCAN is transmitting and receiving CAN frames.
48.5 Initialization/Application Information
This section provide instructions for initializing the FlexCAN module.
48.5.1 FlexCAN Initialization Sequence
The FlexCAN module may be reset in three ways:
• MCU level hard reset, which resets all memory mapped registers asynchronously
• MCU level soft reset, which resets some of the memory mapped registers
synchronously (refer to Table 48-2 to see what registers are affected by soft reset)
• SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.