K60P100M100SF2RM Datasheet, PDF (614/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register descriptions
27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SL)
The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are
numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x
denotes the way, y denotes the set, and U and L represent upper and lower word,
respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets
(n=0-7) in way 2.
Addresses: FMC_DATAW2S0L is 4001_F000h base + 284h offset = 4001_F284h
FMC_DATAW2S1L is 4001_F000h base + 28Ch offset = 4001_F28Ch
FMC_DATAW2S2L is 4001_F000h base + 294h offset = 4001_F294h
FMC_DATAW2S3L is 4001_F000h base + 29Ch offset = 4001_F29Ch
FMC_DATAW2S4L is 4001_F000h base + 2A4h offset = 4001_F2A4h
FMC_DATAW2S5L is 4001_F000h base + 2ACh offset = 4001_F2ACh
FMC_DATAW2S6L is 4001_F000h base + 2B4h offset = 4001_F2B4h
FMC_DATAW2S7L is 4001_F000h base + 2BCh offset = 4001_F2BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW2SnL field descriptions
Field
31–0
data[31:0]
Bits [31:0] of data entry
Description
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
614
Freescale Semiconductor, Inc.