K60P100M100SF2RM Datasheet, PDF (432/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
Memory controller
Memory array
Table 21-2. Transfer control descriptor memory
Submodule
Description
This logic implements the required dual-ported controller,
managing accesses from the eDMA engine as well as
references from the internal peripheral bus. As noted earlier,
in the event of simultaneous accesses, the eDMA engine is
given priority and the peripheral transaction is stalled.
TCD storage is implemented using a single-port,
synchronous RAM array.
21.1.3 Features
The eDMA is a highly-programmable data-transfer engine optimized to minimize the
required intervention from the host processor. It is intended for use in applications where
the data size to be transferred is statically known and not defined within the data packet
itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 16-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16-byte burst transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
432
Freescale Semiconductor, Inc.