K60P100M100SF2RM Datasheet, PDF (704/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
FB_CSCRn field descriptions (continued)
Field
9
BLS
Description
The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge is
generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states).
If AA is reserved, FB_TA must be asserted by the external system regardless of the number of generated
wait states. In that case, the external transfer acknowledge ends the cycle. An external FB_TA
supersedes the generation of an internal FB_TA.
Byte-lane shift
Determines if data on FB_AD appears left-justified or right-justified during the data phase of a FlexBus
access.
0 Not shifted. Data is left-justfied on FB_AD.
1 Shifted. Data is right justified on FB_AD.
8
Auto-acknowledge enable
AA
Determines the assertion of the internal transfer acknowledge for accesses specified by the chip-select
address.
NOTE: If AA is set for a corresponding FB_CSn and the external system asserts an external FB_TA
before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles
increment the address bus between each internal termination.
NOTE: This bit must be set if CSPMCR disables FB_TA.
0 No internal FB_TA is asserted. Cycle is terminated externally
1 Internal transfer acknowledge is asserted as specified by WS
7–6
Port size
PS
Specifies the data port width associated with each chip-select. It determines where data is driven during
write cycles and where data is sampled during read cycles.
5
BEM
00 32-bit port size. Valid data sampled and driven on FB_D[31:0]
01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
Byte-enable mode
Specifies the byte enable operation. Certain memories have byte enables that must be asserted during
reads and writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable
support for these SRAMs.
4
BSTR
0 The FB_BEn signals are not asserted for reads. The FB_BEn signals are asserted for data write only.
1 The FB_BEn signals are asserted for read and write accesses
Burst-read enable
Specifies whether burst reads are used for memory associated with each FB_CSn.
3
BSTW
0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For
example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-
bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
Burst-write enable
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
704
Freescale Semiconductor, Inc.