K60P100M100SF2RM Datasheet, PDF (1462/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
50.4.1.9 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of
a transfer. After the master drives SCL low, a slave can drive SCL low for the required
period and then release it. If the slave's SCL low period is greater than the master's SCL
low period, the resulting SCL bus signal's low period is stretched.
50.4.1.10 I2C Divider and Hold Values
Table 50-41. I2C Divider and Hold Values
ICR
(hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
SCL
Divider
20
22
24
26
28
30
34
40
28
32
36
40
44
48
56
68
48
56
64
72
80
88
104
128
80
SDA Hold SCL Hold SCL Hold
Value
(Start)
(Stop)
Value
Value
7
6
11
7
7
12
8
8
13
8
9
14
9
10
15
9
11
16
10
13
18
10
16
21
7
10
15
7
12
17
9
14
19
9
16
21
11
18
23
11
20
25
13
24
29
13
30
35
9
18
25
9
22
29
13
26
33
13
30
37
17
34
41
17
38
45
21
46
53
21
58
65
9
38
41
ICR
(hex)
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
SCL
Divider
(clocks)
160
192
224
256
288
320
384
480
320
384
448
512
576
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
SDA Hold SCL Hold SCL Hold
(clocks) (Start)
(Stop)
Value
Value
17
78
81
17
94
97
33
110
113
33
126
129
49
142
145
49
158
161
65
190
193
65
238
241
33
158
161
33
190
193
65
222
225
65
254
257
97
286
289
97
318
321
129
382
385
129
478
481
65
318
321
65
382
385
129
446
449
129
510
513
193
574
577
193
638
641
257
766
769
257
958
961
129
638
641
Table continues on the next page...
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.