K60P100M100SF2RM Datasheet, PDF (1676/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
53.1.1 Block diagram
The following figure illustrates the organization of the I²S. It consists of control registers
to set up the port, status register, separate transmit and receive circuits with FIFO
registers, and separate serial clock and frame sync generation for the transmit and receive
sections. The second set of Tx and Rx FIFOs replicates the logic used for the first set of
FIFOs.
Peripheral Bus
32-bit
Transmit Clock
Control Reg
TCCR
Receive Clock
Control Reg
RCCR
Transmit
Config Reg
TCR
Receive
Config Reg
RCR
Control Reg CR
Tx and RX
Control
Tx Clock
Generator
Tx Sync
Generator
Rx Clock
Generator
Rx Sync
Generator
STCK
STFS
SRCK/SYS_CLK
SRFS
Tx and Rx FIFO
and shift register logic
STXD
SRXD
Figure 53-1. Customer-facing I²S block diagram
53.1.2 Features
The I²S includes the following features:
• Independent (asynchronous) or shared (synchronous) transmit and receive sections
with separate or shared internal/external clocks and frame syncs, operating in master
or slave mode.
• Normal mode operation using frame sync
1676
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.