K60P100M100SF2RM Datasheet, PDF (1458/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
50.4 Functional Description
This section provides a comprehensive functional description of the I2C module.
50.4.1 I2C Protocol
The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data
transfers. All devices connected to it must have open drain or open collector outputs. A
logic AND function is exercised on both lines with external pull-up resistors. The value
of these resistors depends on the system.
Normally, a standard instance of communication is composed of four parts:
1. START signal
2. Slave address transmission
3. Data transfer
4. STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The following
figure illustrates I2C bus system communication.
MSB
LSB
SCL
12 3456789
MSB
LSB
1 2 3456789
SDA
AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 R /W
XXX D7 D6 D5 D4 D3 D2 D1 D0
Start Signal
C alling A ddress
R e a d / Ack
W rite ^Bit
MSB
LSB
SCL
1 2 3456789
D ata B yte
No Stop
Ack Signal
Bit
MSB
LSB
1 2 3456789
SDA
AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 R /W
XX
AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 R /W
Start
Signal
C alling A ddress
R e a d / Ack
W rite Bit
Repeated
Start
Signal
N ew C alling A ddress
Figure 50-38. I2C Bus Transmission Signals
Read/
W rite
No _Stop
Ack _Signal
Bit
1458
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.