K60P100M100SF2RM Datasheet, PDF (400/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
module address, transfer attributes, byte enables, and write data as inputs to the
peripherals. The peripheral bridge captures read data from the peripheral interface and
drives it to the crossbar switch.
The register maps of the peripherals are located on 4 KB boundaries. Each peripheral is
allocated one 4 KB block of the memory map.
The peripheral bridge (AIPS-Lite) memory map is illustrated as follows.
Addresses
Base + 0x000_0000 - 0x000_0FFF
Base + 0x000_1000 - 0x000_1FFF
...
Base + 0x007_F000 - 0x007_FFFF
Description
Module #0
Module #1
...
Module #127
19.2 Memory map/register definition
The peripheral bridge registers are 32-bit registers and can only be accessed in supervisor
mode by trusted bus masters. Additionally, these registers must only be read from or
written to by a 32-bit aligned access. The peripheral bridge registers are mapped into the
PACR0 address space.
Two system clocks are required for read accesses, and three system clocks are required
for write accesses to the peripheral bridge registers.
NOTE
The number of fields and registers available depends on the
device-specific implementation of the peripheral bridge
module. See the Chip Configuration chapter for more
information.
AIPS memory map
Absolute
address
(hex)
Register name
4000_0000 Master Privilege Register A (AIPS0_MPRA)
4000_0020 Peripheral Access Control Register (AIPS0_PACRA)
4000_0024 Peripheral Access Control Register (AIPS0_PACRB)
4000_0028 Peripheral Access Control Register (AIPS0_PACRC)
4000_002C Peripheral Access Control Register (AIPS0_PACRD)
Width
(in bits)
Access
Reset value
Section/
page
32
R/W Undefined 19.2.1/401
32
R/W 4444_4444h 19.2.2/405
32
R/W 4444_4444h 19.2.2/405
32
R/W 4444_4444h 19.2.2/405
32
R/W 4444_4444h 19.2.2/405
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
400
Freescale Semiconductor, Inc.